A memory module such as a DIMM (Dual Inline Memory Module) has a configuration in which a plurality of memory chips such as DRAMs (Dynamic Random Access Memories) are mounted on a module board. The memory module is installed in a memory slot on a motherboard. Data transfer is performed between the memory module and a memory controller. Recently, it has become difficult to ensure a required memory capacity using one memory module due to an increase in the memory capacity demanded for a system. For this reason, it is a common practice that the motherboard has a plurality of memory slots, and a plurality of memory modules are installed in the plurality of memory slots. When the plurality of memory modules are installed, the load capacitance of a data line on the motherboard is increased and signal quality of the data line deteriorates. When a data transfer rate between the memory controller and the memory module is increased, there arises a problem that data transfer cannot be properly performed due to deterioration of signal quality caused by the load capacitance of the data line. In order to achieve high-speed data transfer on the order of 1.6 to 3.2 Gbps, for example, the load capacitance of the data line on the motherboard needs to be sufficiently reduced.
As a memory module in which the load capacitance of a data line can be reduced, a so-called Fully-Buffered type memory module is known (refer to Patent Document 1). In the Fully-Buffered type memory module, write data supplied from a memory controller is temporarily received by a dedicated chip referred to as an Advanced Memory Buffer (AMB), and the write data is supplied to a preset memory chip from the AMB. A read operation is opposite to the operation described above. All of read data output from a memory chip is temporarily supplied to the AMB, and is then supplied to the memory controller from the AMB.
Since the memory chip is not directly connected to the memory controller in the Fully-Buffered-type memory, the load capacitance of the data line of the memory chip cannot be seen from the memory controller (only the load capacitance of the AMB can be seen from the memory controller). As a result, the load capacitance of the data line connected to memory controller is greatly reduced.
However, since the AMB used in the Fully-Buffered-type memory module is a high-performance chip, the AMB is comparatively expensive and the power consumption of the AMB is also large. For this reason, there is a problem that the cost of the memory module greatly increases. Further, in the Fully-Buffered type memory module, an interface between the memory controller and the AMB (obtained by serialization and Point-to-Point connection of the interface between each of the modules) is different from a commonly used interface between the memory controller and the memory chip. Thus, there is also a problem that an off-the-shelf memory controller as it is cannot be used.
Under such a background, in recent years, a memory module referred to as a “Load Reduced type” (termed as an “LR-DIMM”) has been proposed. In the LR-DIMM, a memory buffer is used in place of the AMB, and transferred data (DQ), a CA signal inclusive of command and address signals and so forth are buffered. An interface between a memory controller and the memory buffer is not changed from the common interface between the memory controller and a memory chip. Thus, low power consumption is achieved, and an off-the-shelf memory controller as it is can be used. FIG. 1 is a schematic diagram illustrating a configuration of the LR-DIMM. FIG. 1A shows the configuration of the LR-DIMM in the form of a perspective view, and a partially enlarged view in the vicinity of the memory buffer. FIG. 1B shows a side view of the configuration of the LR-DIMM. The configuration shown in FIG. 1 is set to have 3 DPC (DIMMs Per Channel)×3 channels. Namely, the LR-DIMM in FIG. 1 has 3 channels with 3 DIMMs per channel. Reference numeral 101 denotes a motherboard, reference numeral 102 denotes a memory controller, reference numeral 103 denotes a LR-DIMM (DIMM board), reference numeral 104 denotes a memory buffer on the DIMM103, reference numeral 105 denotes a DRAM (clock synchronous type DRAM) on the DIMM 103, reference numeral 106 denotes a data main bus (DQ MAIN bus) on the motherboard 101, reference numeral 107 denotes a DQ stub on the DIMM 103, reference numeral 108 denotes a stub resistor on the DIMM 103, and reference numeral 109 denotes a connector.
Referring to FIG. 1, the DIMM (LR-DIMM) 103 has DRAM chips 105 mounted on both surfaces of the DIMM board. One memory buffer 104 is provided for a plurality of the DRAM chips 105. The memory buffer (also termed as registered buffer) 104 captures each of data signal DQ, control signal CLTL and clock signal CLK which are supplied from the memory controller 102 through the connector 109, stub resistor 108, and DQ stub 107 on the DIMM 103, and performs wave-form shaping and amplification/buffering of each signal of DQ and so forth in synchronization with a timing of the clock signal to supply the resulting signal to the DRAM chip 105 on the DIMM 103.
FIG. 2 is a diagram showing flows of data signal DQ, data strobe signal DQS, CA (command, address) signal, CTRL signal, and clock signal CLK in the LR-DIMM 103 in FIG. 1. The signal indicated by a solid line indicates a (pre-buffered) signal before buffered by the memory buffer 104, and the signal indicated by a broken line indicates a (post-buffered) signal after buffered. The LR-DIMM 103 in FIG. 2 is set to have a 2R×4 configuration (where 2R indicates 2 ranks, while ×4 indicates a 4-bit chip), for example. The memory buffer 104 is arranged on one side of the DIMM board 103, on the other side of which DRAMs 1 are provided at the region opposed to the memory buffer 104. The memory buffer 104 supplies the buffered clock, buffered CA, buffered CTRL and buffered DQ signals to DRAMs 2 to 5 on the one side of the DIMM board 103, and supplies the buffered clock, buffered CA, buffered CTRL and buffered DQ signals to the DRAM 1 on the other side of the DIMM board 103 and the DRAMs 2 to 5 via through-holes.    [Patent Document 1]    JP Patent Kokai Publication No. JP-P2008-135597A